Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Juniper Networks (NYSE: JNPR) has utilized Cadence® Innovus™ Implementation System to improve turnaround time (TAT) for physical implementation of their most complex 28-nanometer (nm) intellectual property (IP) for networking applications. The networking company was able to achieve throughput of more than 1.8 million cells per day while also improving out-of-the-box design performance by 15 percent.
The Innovus Implementation System incorporates the advanced new GigaPlace placement engine and multi-threaded placement optimization, which enabled Juniper Networks to meet its critical performance parameters. The full-flow multi-threading enhancements enabled full utilization of 8- and 16-CPU machines that resulted in the optimal throughput on the multi-million-cell high-performance networking IP blocks.
"We needed to create larger blocks on the last chip, but the excessive turnaround time with our previous tool made this impractical with our aggressive design schedule," said Debashis Basu, SVP Engineering, Silicon and Systems Engineering at Juniper Networks. "Our next system-on-chip (SoC) projects will be on a 16nm process, and the Innovus Implementation System can enable much larger blocks than previously possible, decreasing area and top-level complexity."
"Designs with just a few issues can cost customers a month in the design schedule by the time the problems are discovered, fixed and then rerun," said Dr. Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. "The Innovus Implementation System is helping Juniper Networks to decrease the time to a clean design by getting high-quality results into the designer's hands much sooner. As Juniper embarks on its new 16nm SoC designs, the Innovus Implementation System can provide the desired turnaround time required to meet tight deadlines while improving overall engineering productivity."
The Innovus Implementation System is a next-generation physical implementation solution that enables developers to deliver high-quality designs with best-in-class power, performance, and area (PPA) while accelerating time to market.
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